The present invention relates to semiconductor devices and their methods of manufacture wherein the semiconductor devices have implanted interconnections which are hidden and/or camouflaged so as to inhibit or prevent reverse engineering of the semiconductor device.
The design and development of semiconductor Integrated Circuits (ICs) tends to be rather expensive and, in fact, many hours of engineering talent are required to develop the complex structures, processes and manufacturing techniques involved in making modern semiconductor devices and ICs. Indeed, semiconductor ICs over the years have tended to become more complex and therefore the effort involved in achieving a successful design has become very expensive. Many man-hours of highly skilled professional time are required at considerable expense to design and develop a modem integrated circuit.
Others, in order to avoid not only the expense involved in the design and development of integrated circuits, but also to avoid the significant time involved in bringing a new integrated circuit design to the market place, resort to reverse engineering practices for existing integrated circuits to take apart, probe, and otherwise examine these existing ICs to try to determine the physical structures and methods used to make the integrated circuit for subsequent copying. This reverse engineering, which typically relies primarily on obtaining planar optical images of a circuit, in essence tries to bypass the typical product development cycles and expenses involved in producing integrated circuits.
Since the reverse engineer is trying to go for a xe2x80x9cfree ridexe2x80x9d on the efforts of others, various approaches have been developed to try to thwart the reverse engineer, particularly in the field of semiconductor integrated circuits. See, for example, U.S. Pat. No. 4,583,011 wherein the device is given a depletion implant that is virtually invisible to a reverse engineer.
Integrated circuits typically comprise a large number of active devices, typically in the form of transistors, diodes, and the like, which are interconnected by the means of interconnects. The interconnects are often provided by metallic structures which are formed on various levels within an integrated circuit device. Since these metallic structures etch away in the presence of an appropriate etchant at a different rate compared to the other structures found in a semiconductor device (such as semiconducting material, insulating material, and the like), the reverse engineer can discover the presence and the structure of metallic conductors used to interconnect the active devices in an integrated circuit by putting the needed time and energy into the reverse engineering task. However, since this time and energy is less than that required to design a new IC, reverse engineering has its followers. Indeed, the reverse engineer""s object is to make a working, slavish copy of the original IC and the reverse engineer cares little about how the original IC was designed. The reverse engineer does not seem to be deterred by the fact that in many countries existing ICs are legally protected against copying by some form of mask works protection. As such, in order to protect the considerable investment made in new IC designs, other or additional steps are needed to deter such slavish copying.
The present invention provides a method and apparatus for preventing reverse engineering of integrated circuits by hiding interconnects between various devices and structures (for example, diodes, transistors, input/output connections, power supply connections and the like) so as to make it much more difficult for the reverse engineer to determine how the devices and structures, which can be seen on an integrated circuit, are interconnected.
In one aspect, the present invention provides an interconnect for interconnecting two spaced-apart implanted regions of a common conductivity type in an integrated circuit or device. The interconnect comprises a first implanted region forming a conducting channel between the two spaced-apart implanted regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second implanted region of opposite conductivity type, the second implanted region being disposed between the two spaced-apart implanted regions of common conductivity type and being disposed over the conducting channel.
In another aspect the present invention provides a method of providing and camouflaging an interconnect between two adjacent implanted regions in an integrated circuit or device, the two adjacent implanted regions being of a common conductivity type. The method includes implanting a first region of the same common conductivity type, the first region being disposed between locations where said two adjacent implanted regions either have been or will be formed; and implanting a second region of opposite conductivity type to the common conductivity type, the second region over-lying the first region and having a concentration profile normal to a major surface of the integrated circuit or device with a concentration peak closer to the major surface of the semiconductor device than a concentration peak for the first implanted region.